Hidden time model for specification and verification of embedded systems

Embedded systems are application specific digital systems that are usually designed using a microprocessor along with a set of programmable hardware and software components. Since these systems are real-time in nature, specification of temporal constraints is a key issue. We have recently proposed the CFSMcharts language for component-based specification of these systems. However, this proposal had no features to specify quantitative temporal constraints that are crucial to embedded systems specification. In this paper, we propose a new model of time, called hidden time, for specification of temporal constraints in CFSMcharts and contrast it to existing schemes. The proposed scheme is hierarchical and hides away the quantitative temporal constraints from the top level specification. This leads to a simpler style for the specification of these constraints and simpler semantics for the top level specification. Another major contribution of the proposed scheme is that, properties to be verified can be expressed in propositional temporal logic, whereas all the existing schemes have to use first order temporal logic. We also propose a new temporal logic called Hidden Propositional Temporal Logic (HPTL) as a requirement specification language. HPTL is based on the hidden time model and also supports module name qualifiers, which have applicability in a component-based framework. Finally, we propose a scheme for automated verification.